Altera Corporation announces Nios II EDS

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Altera Corporation has announced the immediate availability of version 6.0 of the Nios II embedded processor and the Nios II Embedded Design Suite (EDS).

The Nios II EDS now includes 32-bit, single-precision, IEEE 754-compatible floating-point support and the recently announced Nios II C-to-Hardware Acceleration (C2H) Compiler. Additionally, Altera has updated the Nios II embedded processor to improve designers' productivity when building multiprocessor systems.

"Both the Nios II C2H Compiler and floating-point support deliver increased performance and flexibility to embedded software developers, amplifying the fundamental time-to-market benefits of the Nios II processor as an FPGA-based computing platform," said Altera Marketing Director, Asia Pacific, Louie Leung, "Including these features in version 6.0 of the Nios II processor and EDS extends Altera's leadership in the embedded systems market."

Floating-point support is delivered as a set of Nios II custom instructions. Custom instructions off-load software operations into hardware and provide an extremely flexible option for increasing CPU performance. When selected

by the user, the prebuilt floating-point custom instructions are added into the CPU data path automatically, and all subsequent floating-point operations are evaluated using the dedicated hardware. Fully supported within the software-programming tool chain,
floating-point custom instructions offer a completely transparent programming model to the designer.

The Nios II C2H Compiler is a productivity tool for Nios II users. It can substantially increase embedded software performance, automatically converting performance-critical C language subroutines into hardware accelerators and integrating them into FPGA-based Nios II subsystems.


In addition to the tool chain enhancements, the Nios II processor now includes top-level synchronization signals to give designers more flexibility in managing multiprocessor system "bring-up." Designers now have an option of using a processor-only reset signal to control the order in which the Nios II processors boot.


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